TPS2202AI

DUAL-SLOT PC CARD POWER-INTERFACE SWITCH

WITH RESET FOR SERIAL PCMCIA CONTROLLER

SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998

17

POST OFFICE BOX 655303

POST OFFICE BOX 1443

APPLICATION INFORMATION

logic input and outputs

The serial interface consists of DATA, CLOCK, and LATCH leads. The data is clocked in on the positive leading

edge of the clock (see Figure 2). The 9-bit (D0 through D8) serial data word is loaded during the positive edge

of the latch signal. The latch signal should occur before the next positive leading edge of the clock.

quiescent current to 1

µA to conserve battery power.

The TPS2202AI serial interface is designed to be compatible with serial-interface PCMCIA controllers and

current PCMCIA and Japan Electronic Industry Development Association (JEIDA) standards.

previously discussed.