ADS54RF63IPFPR datasheet(12/48 Pages) TI

12 / 48 page

ADS5463

ADS54RF63

SLAS515E – NOVEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com

Table 1. PIN FUNCTIONS

DESCRIPTION

NAME

NO.

AIN

Differential input signal (positive)

AIN

Differential input signal (negative)

3, 8, 13, 14, 19, 21,

AVDD5

Analog power supply (5 V)

23, 25, 27, 31

Analog power supply (3.3 V) (Suggestion for

≤250 MSPS: leave option to connect to 5 V for

AVDD3

35, 37, 39

ADS5440/4 13-bit compatibility)

DVDD3

1, 51, 66

Output driver power supply (3.3 V)

7, 9, 12, 15, 18, 20,

AGND

22, 24, 26, 28, 30,

Analog ground

32, 34, 36, 38, 40

(Power Pad)

(81)

Power pad for thermal relief, also analog ground

DGND

2, 52, 65

Digital ground

CLK

Differential input clock (positive). Conversion is initiated on rising edge.

CLK

Differential input clock (negative)

54, 56, 58, 60, 62,

D0–D11

64, 68, 70, 72, 74,

76, 78

LVDS digital output pairs (D0/D0 is LSB pair. D11/D11 is MSB pair.)

53, 55, 57, 59, 61,

D0–D11

63, 67, 69, 71, 73,

75, 77

DRY, DRY

80, 79

Data ready LVDS output pair

No connect (4 and 5 should be left floating, 43–50 are possible future bit additions for this pinout

4, 5, 43–50

and therefore can be connected to a digital bus or left floating)

Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale

OVR, OVR

42, 41

range.

Pin 29 is reserved for possible future Vcm output for this pinout, like ADS5474; pin 33 is reserved for

RESERVED

29, 33

possible future power-down control pin for this pinout, like ADS5474.

VREF

Reference voltage input/output (2.4 V nominal). Connect 0.1-

µF capacitor from VREF to AGND.

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