TVP3703

VIDEO INTERFACE PALETTE

TRUE-COLOR CMOS RAMDAC

SLAS100 – MARCH 1996

15

POST OFFICE BOX 655303

timing requirements

micro port

PARAMETER

TVP3703-170

TVP3703-135

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

tw(WLWH)

Pulse duration, WR low

50

75

ns

tw(RLRH)

Pulse duration, RD low

50

50

ns

trec(WHWL) Recovery time preceding a write (see Notes 6 and 7)

3

×tc(CHCH)

3

×tc(CHCH)

ns

trec(RHRL)

Recovery time preceding a read (see Notes 6 and 7)

6

×tc(CHCH)

6

×tc(CHCH)

ns

tsu(SVL)

Setup time, RS0-RS2

10

10

ns

th(LSX)

Hold time, RS0-RS2

4

4

ns

tsu(DVWH)

Setup time, write data

10

10

ns

th(WHDX)

Hold time, write data

10

10

ns

NOTES:

6. tc(CHCH) (PCLK period) is specified in the pixel port timing requirements table.

7. Access recovery times are specified as the time before a particular access because the worst case access (reading a red palette

color value) can occur after either reading a blue palette color value or after writing to the address register (read mode).

PLL frequency select

PARAMETER

TVP3703-170

TVP3703-135

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

tw(SHSL)

Pulse duration, STROBE high

50

50

ns

tw(SLSH)

Pulse duration, STROBE low

50

50

ns

tsu(SVSL)

Setup time, VS0 –VS3 (see Note 8)

20

30

ns

th(SLSX)

Hold time, VS0 – VS3 (see Note 8)

20

30

ns

NOTE 8: The VS0 – VS3 latches are transparent when STROBE is at logic 1.

pixel port

PARAMETER

TVP3703-170

TVP3703-135

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

PCLK cycle time (pixel mode 05h – double 8-bit, indexed)

11.7

14.8

ns

tc(CHCH)

PCLK cycle time (pixel mode 09h – double 24-bit, direct)

9.08

9.08

ns

()

PCLK cycle time (all other pixel modes)

9.08

9.08

ns

tw(CLCH)

Pulse duration, PCLK low

2.9

4

ns

tw(CHCL)

Pulse duration, PCLK high

2.9

3

ns

tsu(PVCH)

Setup time, pixel data (see Note 9)

2

2

ns

th(CHPX)

Hold time, pixel data (see Note 9)

2

2

ns

NOTE 9: The pixel address input to the color palette should be set up as a valid logic level with the appropriate setup and hold times to each rising

edge of PCLK (this requirement must also be met during the blanking period).