XIO2001 datasheet(9/131 Pages) TI

9 / 131 page

XIO2001 PCI Express™ to PCI Bus Translation Bridge

www.ti.com

SCPS212B – MAY 2009 – REVISED JULY 2009

5-9

Secondary Uncorrectable Error Mask Register Description

............................................................... 103

5-10

Secondary Uncorrectable Error Severity Register Description

........................................................... 104

5-11

Secondary Error Capabilities and Control Register Description

........................................................... 105

5-12

Secondary Header Log Register Description

................................................................................ 106

6-1

Device Control Memory Window Register Map

............................................................................. 107

6-2

GPIO Control Register Description

............................................................................................ 108

6-3

GPIO Data Register Description

............................................................................................... 109

6-4

Serial-Bus Slave Address Register Descriptions

............................................................................ 110

6-5

Serial-Bus Control and Status Register Description

........................................................................ 111

6-6

Serial IRQ Mode Control Register Description

.............................................................................. 112

6-7

Serial IRQ Edge Control Register Description

............................................................................... 113

6-8

Serial IRQ Status Register Description

....................................................................................... 114

6-9

Pre-Fetch Agent Request Limits Register Description

...................................................................... 116

6-10

Cache Timer Transfer Limit Register Description

........................................................................... 117

6-11

Cache Timer Lower Limit Register Description

.............................................................................. 118

6-12

Cache Timer Upper Limit Register Description

.............................................................................. 118

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