STA2064 datasheet(14/19 Pages) STMICROELECTRONICS

14 / 19 page

System features introduction

STA2064

14/19

Doc ID 16057 Rev 1

3.4

Power states

The following power states are defined:

●

OFF: Vdd_on and Vdd are not applied (all data in the backup RAM is lost): no data

retention is kept in the SDRAM

●

NORMAL: Each peripheral runs at its nominal speed with the possibility of turning off

all the unused peripherals (peripheral kernel clock gated)

●

SLOW: PLL1 bypassed. ARM and bus runs at crystal clock. PLL2 runs at its nominal

speed. PLL1 can be optionally put in power down

●

DOZE: It is like SLOW mode with the ARM running either at 19 MHz or 32 kHz

●

STANDBY: PLLs run at their nominal speed. Clocks are gated, ARM in WFI (Wait For

Interrupt) state

●

DEEP-SLEEP: Vdd powered off. Vdd_on powered (RTC, few GPIOs, backup RAM) and

clocked at 32 kHz making the wakeup possible. The context is put in the external

SDRAM while in self refresh mode. Only the Vddio_on region must be powered

●

SLEEP: It is like the DEEP-SLEEP mode, with the difference that Vdd and Vddio are

also applied and all the PLLs are off (optional for PLL2)

●

BACKUP: It is like DEEP-SLEEP, with the difference that the context is not saved in the

external SDRAM. When coming out from Backup to any power state, the ARM core will

execute the first code instruction after 2ms from power on reset release.

While in NORMAL, SLOW AND STANDBY, Vdd_on and Vdd are the same (10% tolerance

between them) and cannot be changed. Also the power to the several IO groups is kept

unchanged.

In order to change the Vdd_on and Vdd values, the system has to transit to either OFF,

SLEEP, DEEP-SLEEP or BACKUP and then back to the selected state.

In order to keep the power consumption as low as possible, the target voltage mentioned in

DEEP-SLEEP is considered at 1.0V.

A dedicated FSM manages the power state transitions among NORMAL, SLOW, DOZE

AND SLEEP. All other states mentioned above are SW variants of the ones managed by the

FSM.

Table 3 shows the summary of the power states supported by STA2064.

Table 3.

Power mode states

Power State

32 kHz

PLL1

PLL2

Vdd_on

Vdd

IOs

OFF

off

NORMAL

1.2V to 1.3V

=Vdd_on

1.7 to 3.6V

SLOW

Off. Bypassed by

main oscillator

off (SW can

take it on)

1.2V to 1.3V

=Vdd_on

1.7 to 3.6V

DOZE

Off. Bypassed by

32 kHz

off (SW can

take it on)

1.2V to 1.3V

=Vdd_on

1.7 to 3.6V

STANDBY

on (clk gated)

ARM in WFI

on (clk gated)

1.2V to 1.3V

=Vdd_on

1.7 to 3.6V

SLEEP

off

off (SW can

take it on)

1.2V to 1.3V

(typically 1.25V)

=Vdd_on

1.7 to 3.6V

STA2064 데이터시트(PDF) 14 Page - STMicroelectronics

STA2064 데이터시트(HTML) 14 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

데이터시트 다운로드

링크 URL