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LTM9002 데이터시트(PDF) 6 Page - Linear Technology

부품명 LTM9002
상세설명  14-Bit Dual-Channel IF/Baseband Receiver Subsystem
PDF  28 Pages
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제조업체  LINER [Linear Technology]
홈페이지  http://www.linear.com
Logo LINER - Linear Technology

LTM9002 데이터시트(HTML) 6 Page - Linear Technology

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LTM9002
6
9002f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: OVDD = VCC = VDD = 3V, fSAMPLE = MAX, input range = VIN
with differential drive, CLKA = CLKB, VINCM = 1.25V, AMPSHDN =
ADCSHDN = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fS
Sampling Frequency
LTM9002-AA
l
1
125
MHz
LTM9002-LA
l
1
65
MHz
tL
CLK Low Time
Duty Cycle Stabilizer Off (Note 6), LTM9002-AA
Duty Cycle Stabilizer On (Note 6), LTM9002-AA
l
l
3.8
3
4
4
500
500
ns
ns
tH
CLK High Time
Duty Cycle Stabilizer Off (Note 6), LTM9002-AA
Duty Cycle Stabilizer On (Note 6), LTM9002-AA
l
l
3.8
3
4
4
500
500
ns
ns
tL
CLK Low Time
Duty Cycle Stabilizer Off (Note 6), LTM9002-LA
Duty Cycle Stabilizer On (Note 6), LTM9002-LA
l
l
7.3
5
7.7
7.7
500
500
ns
ns
tH
CLK High Time
Duty Cycle Stabilizer Off (Note 6), LTM9002-LA
Duty Cycle Stabilizer On (Note 6), LTM9002-LA
l
l
7.3
5
7.7
7.7
500
500
ns
ns
tAP
Absolute Aperture Delay
0ns
tD
CLK to DATA Delay
CL = 5pF (Note 6)
l
1.4
2.7
5.4
ns
tC
CLK to CLKOUT Delay
CL = 5pF (Note 6)
l
1.4
2.7
5.4
ns
DATA to CLKOUT Skew
(tD – tC) (Note 6)
l
–0.6
0
0.6
ns
tMD
MUX to DATA Delay
CL = 5pF (Note 6)
l
1.4
2.7
5.4
ns
DATA Access Time After OE
↓
CL = 5pF (Note 6)
l
4.3
10
ns
BUS Relinquish Time
(Note 6)
l
3.3
8.5
ns
Pipeline Latency
5
Cycles
SPI Interface for Aux DACs, VDD = 2.7V to 3.6V
t1
SDI Valid to SCK Setup
4
ns
t2
SDI Valid to SCK Hold
4
ns
t3
SCK High Time
9ns
t4
SCK Low Time
9ns
t5
CS/LD Pulse Width
10
ns
t6
LSB SCK High to CS/LD
7
ns
t7
CS/LD Low to SCK High
7
ns
t10
CS/LD High to SCK Positive Edge
7
ns
SCK Frequency 50% Duty Cycle
50
MHz
The
l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 6) (Not applicable for LTM9002-LA)
TIMING CHARACTERISTICS
Note 4: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 5: Offset error is the output code resulting when the inputs are
shorted together. The output code is converted to millivolts.
Note 6: Guaranteed by design, not subject to test.
Note 7: VDD = 3V, fSAMPLE = MAX, input range = VIN with differential drive.
The supply current and power dissipation are the sum total for both
channels with both channels active.



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