2

REV. 1B October 2003

DATA SHEET

SPT7851

Electrical Specifications

Bias1 = 90µA, Bias2 = 9.5µA, Differential Input, Duty Cycle = 50%; unless otherwise noted)

Parameter

Conditions

Test Level

Min

Typ

Max

Units

DC Accuracy

Resolution

10

Bits

Differential Linearity

V

±0.6

LSB

Integral Linearity

V

±0.75

LSB

No Missing Codes

VI

Analog Input

Input Voltage Range (differential)

IV

±0.6

±1.0

±1.7

V

Common Mode Input Voltage

IV

1.2

1.65

1.9

V

Input Capacitance

V

1.4

pF

Input Bandwidth (large signal)

V

120

MHz

Offset (mid-scale)

V

±1.0

%FSR

Gain Error

V

0.3

%FSR

Reference Voltages

Reference Input Voltage Range

IV

0.6

1.0

1.7

V

0.9

1.0

1.3

V

1.9

2.0

2.9

V

1.3

1.65

1.8

V

V

35

µA

V

-25

µA

Switching Performance

Maximum Conversion Rate

VI

20

MHz

Pipeline Delay (see Figure 1)

IV

7.5

CLK

5

ns

Aperture Jitter Time

V

10

ps-rms

Dynamic Performance

Signal-To-Noise Ratio

VI

57

58

dB

V

58

dB

Effective Number of Bits

VI

9.0

9.3

Bits

V

9.0

Bits

Total Harmonic Distortion

VI

-68

-61

dB

V

-60

dB

Signal-To-Noise and Distortion

VI

56

58

dB

V

56

dB

Spurious Free Dynamic Range

VI

62

70

dB

V

61

dB

Differential Phase

V

0.2

deg

Differential Gain

V

0.5

%

Guaranteed