TMC22091 datasheet(39/60 Pages) CADEKA

39 / 60 page

PRODUCT SPECIFICATION

TMC22091/TMC22191

Internal Pixel Data Control

When programmed as an output, PDC goes HIGH four

PXCK periods prior to the end of CBP (as programmed in

the horizontal timing registers) which is also four PXCK

cycles prior to required input of the ﬁrst pixel of a line.

Pixels produced by the encoder appear at the analog outputs

(COMPOSITE, LUMA, CHROMA) 40 clocks after they are

registered into the PD port. Note that the pixels enter at one-

half the PXCK rate. The encoded signal passes through

interpolation ﬁlters which generate intermediate output val-

ues, improving the output frequency response and greatly

simplifying the external reconstruction ﬁlter. The interpo-

lated pixels are designated PI in the diagram.

Figure 17. External Pixel Data Control

PXCK

24358A

COMPOSITE

OUTPUT

POST-FILTER

OUTPUT

PDC

P19

P20

P22

P23

P24

PI1 P2 PI2 P3

P21

Figure 18. Internal Pixel Data Control

PXCK

tDO

24357A

COMPOSITE

OUTPUT

POST-FILTER

OUTPUT

PDC

P19

P20

P22

P23

P24

PI1 P2 PI2 P3

P21

TMC22091 데이터시트(PDF) 39 Page - Cadeka Microcircuits LLC.

TMC22091 데이터시트(HTML) 39 Page - Cadeka Microcircuits LLC.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

데이터시트 다운로드

링크 URL