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CS2000-OTP 데이터시트(PDF) 17 Page - Cirrus Logic

부품명 CS2000-OTP
상세설명  Fractional-N Clock Synthesizer & Clock Multiplier
PDF  30 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS2000-OTP 데이터시트(HTML) 17 Page - Cirrus Logic

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CS2000-OTP
DS758F1
17
5.4.6
Ratio Configuration Summary
The RUD is the user defined ratio for which up to four different values (Ratio0-3) can be stored in the one
time programmable memory. The M[1:0] pins or LockClk[1:0] modal parameter then select the user de-
fined ratio to be used (depending on if static or dynamic ratio mode is to be used). The resolution for the
RUD is selectable for the dynamic ratio mode. R-Mod is applied accordingly. The user defined ratio, ratio
modifier, and automatic ratio modifier make up the effective ratio REFF, the final calculation used to deter-
mine the output to input clock ratio. The effective ratio is then corrected for the internal dividers. The fre-
quency synthesizer’s fractional-N source selection is made between the static ratio (in frequency
synthesizer mode) or the dynamic ratio generated from the digital PLL (in Hybrid PLL mode) by either the
FracNSrc modal parameter for manual mode or the presence of CLK_IN in automatic mode. The concep-
tual diagram in Figure 13 summarizes the features involved in the calculation of the ratio values used to
generate the fractional-N value which controls the Frequency Synthesizer. The subscript ‘4’ indicates the
modal parameters.
Figure 13. Ratio Feature Summary
Referenced Control
Parameter Definition
Ratio 0-3................................“Ratio 0 - 3” on page 23
M[1:0] pins............................. “M1 and M0 Mode Pin Functionality” on page 19
LockClk[1:0] .......................... “Lock Clock Ratio (LockClk[1:0])” section on page 23
LFRatioCfg ............................ “Low-Frequency Ratio Configuration (LFRatioCfg)” on page 24
RModSel[1:0] ........................ “R-Mod Selection (RModSel[1:0])” section on page 22
RefClkDiv[1:0] ....................... “Reference Clock Input Divider (RefClkDiv[1:0])” on page 24
FracNSrc ............................... “Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page 23
Effective Ratio REFF
Ratio Format
Frequency Reference Clock
(CLK_IN)
SysClk
PLL Output
Frequency
Synthesizer
Digital PLL &
Fractional N Logic
R Correction
N
Ratio 0
Ratio 1
Ratio 2
Ratio 3
12.20
20.12
12.20
only
M[1:0] pins
LockClk[1:0]4
LFRatioCfg
Ratio
Modifier
RModSel[1:0]4
Ratio
Modifier
Auto Selection
(CLK_IN sense)
Manual Selection
(FracNSrc4 or M2 pin)
R Correction
RefClkDiv[1:0]
Timing Reference Clock
(XTI/REF_CLK)
Divide
RefClkDiv[1:0]
Static Ratio
Dynamic Ratio
User Defined Ratio RUD
M2 pin force Manual
or
M[1:0] pins =? LockClk[1:0]
≠
=
M2 pin



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