CS5366_09 datasheet(17/42 Pages) CIRRUS

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DS626F4

CS5366

SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMING

Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL = 30 pF

Notes:

Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

Figure 5. I²C Timing

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

fscl

100

kHz

RST Rising Edge to Start

tirs

600

Bus Free Time Between Transmissions

tbuf

4.7

µs

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

µs

Clock Low time

tlow

4.7

Clock High Time

thigh

4.0

Setup Time for Repeated Start Condition

tsust

4.7

SDA Hold Time from SCL Falling

(Note 1)

thdd

SDA Setup time to SCL Rising

tsud

600

Rise Time of SCL and SDA

trc

-1

µs

Fall Time SCL and SDA

tfc

-300

Setup Time for Stop Condition

tsusp

4.7

µs

Acknowledge Delay from SCL Falling

tack

300

1000

buf

hdst

lo w

hdd

high

sud

Stop

Sta rt

SD A

SCL

irs

RS T

hdst

t sust

t susp

Sta rt

Stop

Re p e at e d

ack

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