CS5566

DS806PP2

5

5/4/09

V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 8 MHz; SMODE = VL.;

BUFEN = V1+ unless otherwise stated. Connected per Figure 8.

5.

For optimum performance, VREF+ should always be less than (V+) - 0.2 volts to prevent saturation of the VREF+ input buffer.

6.

Specification is for MCLK = 8MHz and 5 kSps conversion rate. MCLK frequency and conversion rate affect power consumption.

7.

Tested with 100 mVP-P on any supply up to 2 kHz. V1+ and V2+ supplies at the same voltage potential, V1- and V2- supplies at

the same voltage potential.

Parameter

Min

Typ

Max

Unit

Voltage Reference Input

Voltage Reference Input Range

(VREF+) – (VREF-)

(Note 5)

2.4

4.096

4.2

V

Input Capacitance

-

10

-

pF

CVF Current

VREF+ Buffer On (BUFEN = V+)

VREF+ Buffer Off (BUFEN = V-)

VREF-

-

-

-

3

1

1

-

-

-

μA

mA

mA

Power Supplies

Average DC Power Supply Currents (Note 6)

-

-

-

-

-

-

5

0.6

0.4

mA

mA

mA

Peak DC Power Supply Currents

(Note 6)

-

-

-

-

-

-

9

1.2

280

mA

mA

μA

Average Power Consumption

Normal Operation Buffers On

(Note 6)

Buffers Off

Sleep (SLEEP = 0)

-

-

-

20

15

6

-

-

-

mW

mW

mW

Power Supply Rejection

(Note 7)

V1+ , V2+ Supplies

V1-, V2- Supplies

75

75

85

85

-

-

dB

dB