CS5560

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DS713PP2

5/4/09

To perform only one conversion, CONV should return high at least 20 master clock cycles before RDY

falls.

Once a conversion is completed and RDY falls, RDY will return high when all the bits of the data word are

emptied from the serial port or if the conversion data is not read and CS is held low, RDY will go high two

MCLK cycles before the end of conversion. RDY will fall at the end of the next conversion when new data

is put into the port register.

See Serial Port on page 24 for information about reading conversion data.

Conversion performance can be affected by several factors. These include the choice of clock source for

the chip, the timing of CONV, and the choice of the serial port mode.

The converter can be operated from an internal oscillator. This clock source has greater jitter than an ex-

ternal crystal-based clock. Jitter may not be an issue when measuring DC signals, or very-low-frequency

AC signals, but can become an issue for higher frequency AC signals. For maximum performance when

digitizing AC signals, a low-jitter MCLK should be used.

To maximize performance, the CONV pin should be held low in the continuous conversion state to per-

form multiple conversions, or CONV should occur synchronous to MCLK, falling when MCLK falls.

If the converter is operated at maximum throughput, the SSC serial port mode is less likely to cause in-

terference to measurements as the SCLK output is synchronized to the MCLK. Alternately, any interfer-

ence due to serial port clocking can also be minimized if data is read in the SEC serial port mode when a

conversion is not in progress.