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CS5511-ASZ 데이터시트(PDF) 15 Page - Cirrus Logic

부품명 CS5511-ASZ
상세설명  16-bit and 20-bit, 8-pin ?誇 ADCs
PDF  26 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5511-ASZ 데이터시트(HTML) 15 Page - Cirrus Logic

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CS5510/11/12/13
DS337F4
15
CS5511/13 and oscillates at 64 kHz ±32 kHz. The
output word rate (OWR) for the CS5511/13 is de-
rived from the internal oscillator, and is equal to
fosc/612. Due to the part-to-part variances in the
oscillator frequency, the OWR of the CS5511/13
can vary between 53 Sps and 159 Sps.
2.5
Performing Conversions
After power and a clock source are established to
the CS5510/11/12/13, the ADCs begin performing
conversions. The three sections that follow explain
how to read conversion data from each ADC, and
decode the conversion word into the respective
flag and data bits. Keep in mind that in the
CS5510/12, SCLK provides the external clock
source for the converter. Data is clocked from the
CS5510/12 at the rate set by the external clock
source (typically 32.768 kHz). The CS5511/13 pro-
vides an on-chip oscillator for the master clock. In
the CS5511/13, SCLK is asynchronous to the on-
chip oscillator and can be clocked at a rate up to
2MHz.
VD+ = 2.5 V to 5.25 V
To SCLK
Fairchild NC7SU04
or 1/6 74HCU04
22 pF
47 pF
32.768 kHz
49.9 K
Ω
10 M
Ω
Figure 12. External (CMOS Compatible) Clock
Counter/Timer
SCLK
SDO
CS
CS5510/12
µC
Figure 13. Using a Microcontroller as a Clock
0
0.0005
0.001
0.0015
0.002
0.0025
0.003
0.0035
0.004
10
30
50
70
90
110
130
SCLK (kHz)
OWR = SCLK
612
Figure 14. Typical Linearity Error for CS5510.
0
0.0005
0.001
0.0015
0.002
0.0025
0.003
0
20
40
60
80 100 120 140 160 180 200
SCLK (kHz)
OWR = SCLK
612
Figure 15. Typical Linearity Error for CS5512.



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