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AS8SLC128K32Q-25L/XT 데이터시트(PDF) 4 Page - Austin Semiconductor

부품명 AS8SLC128K32Q-25L/XT
상세설명  128K x 32 SRAM SRAM MEMORY ARRAY
PDF  10 Pages
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제조업체  AUSTIN [Austin Semiconductor]
홈페이지  http://www.austinsemiconductor.com
Logo AUSTIN - Austin Semiconductor

AS8SLC128K32Q-25L/XT 데이터시트(HTML) 4 Page - Austin Semiconductor

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SRAM
SRAM
SRAM
SRAM
SRAM
AS8SLC128K32
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
4
AS8SLC128K32
Rev. 0.6 06/05
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(NOTE 5) (-55oC<T
A < 125
oC and -40oC to +85oC; V
CC = 3.3V ±0.3V)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
READ CYCLE
READ cycle time
tRC
10
12
15
17
20
ns
Address access time
tAA
10
12
15
17
20
ns
Chip select access time
tACS
10
12
15
17
20
ns
Output hold from address change
tOH
12222
ns
Chip select to output in Low-Z
tLZCS
12222
ns
4,6,7
Chip select to output in High-Z
tHZCS
5.5
6
7
7.5
8
ns
4,6,7
Output enable access time
tAOE
0
5.5
0607
7.5
0
8
ns
Output enable to output in Low-Z
tLZOE
00000
ns
4,6
Output disable to output in High-Z
tHZOE
5.5
6
7
7.5
8
ns
4,6
WRITE CYCLE
WRITE cycle time
tWC
10
12
15
17
20
ns
Chip select to end of write
tCW
9
10101112
ns
Address valid to end of write
tAW
9
10101112
ns
Address setup time
tAS
00000
ns
Address hold from end of write
tAH
00000
ns
WRITE pulse width, CS\ controlled
tWP1
9
10121415
ns
WRITE pulse width, WE\ controlled
tWP2
9
10121415
ns
Data setup time
tDS
567
7.5
8
ns
Data hold time
tDH
11111
ns
Write disable to output in Low-z
tLZWE
22222
ns
4,6,7
Write enable to output in High-Z
tHZWE
5
5
6
6.5
7
ns
4,6,7
DESCRIPTION
-15
-12
SYMBOL
NOTES
-10
-17
UNITS
-20



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