SN8P2602B datasheet(3/95 Pages) SONIX

3 / 95 page

SN8P2602B

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 3

Preliminary Version 0.4

Table of Content

AMENDMENT HISTORY ............................................................................................................................ 2

PRODUCT OVERVIEW......................................................................................................................... 7

1.1

FEATURES ........................................................................................................................................ 7

1.2

SYSTEM BLOCK DIAGRAM .......................................................................................................... 8

1.3

PIN ASSIGNMENT ........................................................................................................................... 9

1.4

PIN DESCRIPTIONS....................................................................................................................... 10

1.5

PIN CIRCUIT DIAGRAMS............................................................................................................. 11

CENTRAL PROCESSOR UNIT (CPU) .............................................................................................. 12

2.1

MEMORY MAP............................................................................................................................... 12

2.1.1

PROGRAM MEMORY (ROM) ................................................................................................. 12

2.1.1.1

RESET VECTOR (0000H) .................................................................................................. 13

2.1.1.2

INTERRUPT VECTOR (0008H)......................................................................................... 14

2.1.1.3

LOOK-UP TABLE DESCRIPTION.................................................................................... 16

2.1.1.4

JUMP TABLE DESCRIPTION ........................................................................................... 18

2.1.1.5

CHECKSUM CALCULATION........................................................................................... 20

2.1.2

CODE OPTION TABLE ........................................................................................................... 21

2.1.3

DATA MEMORY (RAM)........................................................................................................... 22

2.1.4

SYSTEM REGISTER.................................................................................................................23

2.1.4.1

SYSTEM REGISTER TABLE ............................................................................................ 23

2.1.4.2

SYSTEM REGISTER DESCRIPTION ............................................................................... 23

2.1.4.3

BIT DEFINITION of SYSTEM REGISTER....................................................................... 24

2.1.4.4

ACCUMULATOR ............................................................................................................... 25

2.1.4.5

PROGRAM FLAG ............................................................................................................... 26

2.1.4.6

PROGRAM COUNTER....................................................................................................... 27

2.1.4.7

Y, Z REGISTERS................................................................................................................. 30

2.1.4.8

R REGISTERS ..................................................................................................................... 31

2.2

ADDRESSING MODE .................................................................................................................... 32

2.2.1

IMMEDIATE ADDRESSING MODE....................................................................................... 32

2.2.2

DIRECTLY ADDRESSING MODE .......................................................................................... 32

2.2.3

INDIRECTLY ADDRESSING MODE ...................................................................................... 32

2.3

STACK OPERATION...................................................................................................................... 33

2.3.1

OVERVIEW .............................................................................................................................. 33

2.3.2

STACK REGISTERS .................................................................................................................34

2.3.3

STACK OPERATION EXAMPLE............................................................................................. 35

RESET ..................................................................................................................................................... 36

SN8P2602B 데이터시트(PDF) 3 Page - SONiX Technology Company

SN8P2602B 데이터시트(HTML) 3 Page - SONiX Technology Company

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

데이터시트 다운로드

링크 URL