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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32F101x8 데이터시트(PDF) 65 Page - STMicroelectronics |
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STM32F101x8 데이터시트(HTML) 65 Page - STMicroelectronics |
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65 / 81 page  STM32F101x8, STM32F101xB Electrical characteristics Doc ID 13586 Rev 12 65/81 Figure 29. Typical connection diagram using the ADC 1. Refer to Table 41 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 30 or Figure 31, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 30. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF- inputs are available only on 100-pin packages. ai14139d STM32F10xxx VDD AINx IL±1 µA 0.6 V VT RAIN(1) Cparasitic VAIN 0.6 V VT RADC(1) CADC(1) 12-bit converter Sample and hold ADC converter V REF+ STM32F10xxx V DDA V SSA/V REF- 1 µF // 10 nF 1 µF // 10 nF ai14380b |
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