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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST7263BEx 데이터시트(PDF) 55 Page - STMicroelectronics |
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ST7263BEx 데이터시트(HTML) 55 Page - STMicroelectronics |
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55 / 186 page  ST7263Bxx On-chip peripherals Doc ID 7516 Rev 8 55/186 Figure 26. Watchdog block diagram a Note: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 11.1.4 Software Watchdog option If Software Watchdog is selected by option byte, the watchdog is disabled following a reset. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 11.1.5 Hardware Watchdog option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. 11.1.6 Low power modes WAIT instruction No effect on Watchdog. Table 17. Watchdog timing (fCPU = 8 MHz) CR register initial value WDG timeout period (ms) Max FFh 393.216 Min C0h 6.144 RESET WDGA 7-BIT DOWNCOUNTER fCPU T6 T0 CLOCK DIVIDER WATCHDOG CONTROL REGISTER (CR) ÷49152 T1 T2 T3 T4 T5 |
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