ST7263BEx datasheet(111/186 Pages) STMICROELECTRONICS

111 / 186 page

ST7263Bxx

On-chip peripherals

Doc ID 7516 Rev 8

111/186

When the I²C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.

Figure 47.

I²C interface block diagram

11.5.4

Functional description

Refer to the CR, SR1 and SR2 registers in Section 11.5.7. for the bit definitions.

By default the I²C interface operates in Slave mode (M/SL bit is cleared) except when it

initiates a transmit or receive sequence.

Slave mode

As soon as a start condition is detected, the address is received from the SDA line and sent

to the shift register; then it is compared with the address of the interface or the General Call

address (if selected by software).

●

Address not matched: the interface ignores it and waits for another Start condition.

●

Address matched

The interface generates in sequence:

–

Acknowledge pulse if the ACK bit is set.

–

EVF and ADSL bits are set with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 register, holding the SCL line low (see

Figure 48 Transfer sequencing EV1).

Next, software must read the DR register to determine from the least significant bit (Data

Direction Bit) if the slave must enter Receiver or Transmitter mode.

Slave receiver

DATA REGISTER (DR)

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGISTER (OAR)

CLOCK CONTROL REGISTER (CCR)

STATUS REGISTER 1 (SR1)

CONTROL REGISTER (CR)

CONTROL LOGIC

STATUS REGISTER 2 (SR2)

INTERRUPT

CLOCK CONTROL

DATA CONTROL

SCL or SCLI

SDA or SDAI

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