ST7263BEx datasheet(127/186 Pages) STMICROELECTRONICS

127 / 186 page

ST7263Bxx

On-chip peripherals

Doc ID 7516 Rev 8

127/186

Software procedure

Refer to the control/status register (CSR) and data register (DR) in Section 11.6.6 for the bit

definitions and to Figure 51 for the timings.

ADC configuration

The total duration of the A/D conversion is 12 ADC clock periods (1/fADC=4/fCPU).

The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the

«I/O ports» chapter. Using these pins as analog inputs does not affect the ability of the port

to be read as a logic input.

In the CSR register:

●

Select the CH[3:0] bits to assign the analog channel to be converted.

ADC conversion

In the CSR register:

●

Set the ADON bit to enable the A/D converter and to start the first conversion. From this

time on, the ADC performs a continuous conversion of the selected channel.

When a conversion is complete:

●

The COCO bit is set by hardware.

●

No interrupt is generated.

●

The result is in the DR register and remains valid until the next conversion has ended.

A write to the CSR register (with ADON set) aborts the current conversion, resets the COCO

bit and starts a new conversion.

Figure 51.

ADC conversion timings

11.6.4

Low power modes

Note:

The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced

power consumption when no conversion is needed and between single shot conversions.

ADCCSR WRITE

ADON

COCO BIT SET

tLOAD

tCONV

OPERATION

HOLD

CONTROL

Table 44.

Low power modes

Mode

Description

WAIT

No effect on A/D Converter

HALT

A/D Converter disabled.

After wakeup from Halt mode, the A/D Converter requires a stabilization time

before accurate conversions can be performed.

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