MCP3901 datasheet(36/60 Pages) MICROCHIP

36 / 60 page

MCP3901

DS22192A-page 36

6.7.1

CONTINUOUS WRITE

Both ADCs are powered up with their default

configurations, and begin to output DR pulses

immediately (RESET<1:0> and SHUTDOWN<1:0>

bits are off by default).

The default output codes for both ADCs are all zeros.

The default modulator output for both ADCs is 0011

(corresponding to a theoretical zero voltage at the

inputs). The default phase is zero between the two

channels.

It is recommended to enter into ADC reset mode for

both ADCs just after power-up because the desired

MCP3901 register configuration may not be the default

one and in this case, the ADC would output undesired

data. Within the ADC reset mode (RESET<1:0>=11),

the user can configure the whole part with a single com-

munication.

The

write

commands

increment

automatically the address so that the user can start

writing the PHASE register and finish with the

CONFIG2 register in only one communication (see

Figure 6-6). The RESET<1:0> bits are in the CONFIG2

the whole part configured and ready to run in only one

command.

The following register sets are defined as groups:

The following register sets are defined as types:

6.8

Situations that Reset ADC Data

Immediately after the following actions, the ADCs are

temporarily reset in order to provide proper operation:

Change in PHASE register.

Change in the OSR setting.

Change in the PRESCALE setting.

Overwrite of same PHASE register value.

Change in CLKEXT bit in the CONFIG2 register

modifying internal oscillator state.

After these temporary resets, the ADCs go back to the

normal operation with no need for an additional

command. These are also the settings where the DR

position is affected. The PHASE register can be used

to serially soft reset the ADCs without using the RESET

bits in the configuration register if the same value is

written in the PHASE register.

FIGURE 6-7:

Recommended Configuration Sequence at Power Up.

TABLE 6-1:

GROUP

ADDRESSES

ADC DATA CH0

0x00 - 0x02

ADC DATA CH1

0x03 - 0x05

MOD, PHASE, GAIN

0x06 - 0x08

CONFIG, STATUS

0x09 - 0x0B

TABLE 6-2:

TYPE

ADDRESSES

ADC DATA

(Both Channels)

0x00 - 0x05

CONFIGURATION

0x06 - 0x0B

00011000

SCK

SDI

AVDD

11XXXXXX

CONFIG2 ADDR/W

CONFIG2

Optional RESET of both ADCs

One command for writing complete configuration

PHASE ADDR/W

GAIN

STATUS/COM

CONFIG1

CONFIG2

PHASE

00001110

xxxxxxxx

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