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MCP14700 데이터시트(PDF) 14 Page - Microchip Technology

부품명 MCP14700
상세설명  Dual Input Synchronous MOSFET Driver
PDF  26 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP14700 데이터시트(HTML) 14 Page - Microchip Technology

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MCP14700
DS22201A-page 14
© 2009 Microchip Technology Inc.
5.4
PCB Layout
Proper PCB layout is important in a high current, fast
switching circuit to provide proper device operation.
Improper component placement may cause errant
switching, excessive voltage ringing, or circuit latch-up.
There are two important states of the MCP14700
outputs, high and low. Figure 5-1 depicts the current
flow paths when the outputs of the MCP14700 are high
and the power MOSFETs are turned on. The charge
needed to turn on the low-side power MOSFET comes
from the decoupling capacitor CVCC. The current flows
from this capacitor through the internal LOWDR
circuitry, into the gate of the low-side power MOSFET,
out the source, into the ground plane, and back to
CVCC. To reduce any excess voltage ringing or spiking,
the inductance and area of this current loop must be
minimized.
FIGURE 5-1:
Turn On Current Paths.
The charge needed to turn on the high-side power
MOSFET comes from the bootstrap capacitor CBOOT.
Current flows from CBOOT through the internal
HIGHDR circuitry, into the gate of the high-side power
MOSFET, out the source and back to CBOOT. The
printed circuit board traces that construct this current
loop need to have a small area and low inductance. To
control the inductance, short and wide traces must be
used.
Figure 5-2 depicts the current flow paths when the
outputs of the MCP14700 are low and the power
MOSFETs are turned off. These current paths should
also have low inductance and a small loop area to
minimize the voltage ringing and spiking.
FIGURE 5-2:
Turn Off Current Paths.
The following recommendations should be followed for
optimal circuit performance:
- The components that construct the high
current paths previously mentioned should be
placed close the MCP14700 device. The
traces used to construct these current loops
should be wide and short to keep the
inductance and impedance low.
- A ground plane should be used to keep both
the parasitic inductance and impedance
minimized. The MCP14700 device is capable
of sourcing and sinking high peaks current
and any extra parasitic inductance or
impedance will result in non-optimal
performance.
VCC
PWMHI
CVCC
CBOOT
VSUPPLY
MCP14700
PWMLO
VCC
PWMHI
CVCC
CBOOT
VSUPPLY
MCP14700
PWMLO



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