| 전자부품 데이터시트 검색엔진 |
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PIC18F44J10 데이터시트(PDF) 116 Page - Microchip Technology |
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PIC18F44J10 데이터시트(HTML) 116 Page - Microchip Technology |
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116 / 368 page ![]() PIC18F45J10 FAMILY DS39682E-page 114 © 2009 Microchip Technology Inc. FIGURE 10-4: PARALLEL SLAVE PORT WRITE WAVEFORMS FIGURE 10-5: PARALLEL SLAVE PORT READ WAVEFORMS TABLE 10-13: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 50 LATD(1) PORTD Data Latch Register (Read and Write to Data Latch) 50 TRISD(1) PORTD Data Direction Control Register 50 PORTE(1) — — — — — RE2 RE1 RE0 50 LATE(1) — — — — — PORTE Data Latch Register (Read and Write to Data Latch) 50 TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 50 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 48 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’. Q1 Q2 Q3 Q4 CS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 WR RD IBF OBF PSPIF PORTD<7:0> Q1 Q2 Q3 Q4 CS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 WR IBF PSPIF RD OBF PORTD<7:0> |
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