EBJ41HE4BAFA

Data Sheet E1256E40 (Ver. 4.0)

17

CKE (input pin)

CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers.

Taking CKE low provides precharge power-down and self-refresh operation (all banks idle), or active power-down

(row active in any bank). CKE is asynchronous for self-refresh exit. After VREF has become stable during the

power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper

self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read

and write accesses. Input buffers, excluding CK, /CK, ODT and CKE are disabled during power-down. Input buffers,

excluding CKE, are disabled during self-refresh.

DQ and CB (input and output pins)

Bi-directional data bus.

DQS and /DQS (input and output pin)

Output with read data, input with write data. Edge-aligned with read data, centered in write data.

The data strobe DQS is paired with differential signals /DQS to provide differential pair signaling to the system during

READs and WRITEs.

ODT (input pins)

ODT (registered high) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only

applied to each DQ, DQS, /DQS, DM. The ODT pin will be ignored if the mode register (MR1) is programmed to

disable ODT.

VDD (power supply pins)

1.5V is applied. (VDD is for the internal circuit.)

VDDSPD (power supply pin)

3.3V is applied (For serial EEPROM).

VSS (power supply pin)

Ground is connected.

VTT (power supply pin)

Termination supply.

VREFDQ (power supply)

Reference voltage for DQ.

VREFCA (power supply)

Reference voltage for CA.

SCL (input pin)

Clock input for serial PD.

SDA (input and output pins)

Data input/output for serial PD.

SA (input pin)

Serial address input.

/RESET (input pin)

/RESET is negative active signal (active low) and is referred to GND.