MC33596FCAESLASHR2 datasheet(9/70 Pages) FREESCALE

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MCU Interface

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

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In direct access, the user programs direct all three frequency registers.

MCU Interface

The MC33596 and the MCU communicate via a serial peripheral interface (SPI). According to the selected

mode, the MC33596 or the MCU manages the data transfer. The MC33596’s digital interface can be used

as a standard SPI (master/slave) or as a simple interface (SPI deselected). In the following case, the

interface’s pins are used as standard I/O pins. However, the MCU has the highest priority, as it can control

the MC33596 by setting CONFB pin to the low level. During an SPI access, the STROBE pin must remain

at high level to prevent the MC33596 from entering standby mode.

The interface is operated by six I/O pins.

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CONFB — Configuration control input

The configuration mode is reached by setting CONFB to low level.

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STROBE — Wakeup control input

The STROBE pin controls the ON/OFF sequence of the MC33596. When STROBE is set to low

level, the receiver is off—when STROBE is set to high level, the receiver is on. The current

consumption in receive mode can be reduced by strobing the receiver. The periodic wakeup can be

done by MCU only or by an internal oscillator thanks to an external capacitor (strobe oscillator

must be previously enabled by setting SOE bit to 1). Refer to Section 11.3, “Receiver On/Off

Control,” for more details.

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SEB — Serial interface enable control input

When SEB is set high, pins SCLK, MOSI, and MISO are set to high impedance, and the SPI bus

is disabled. When SEB is set low, SPI bus is enabled. This allows individual selection in a multiple

device system, where all devices are connected via the same bus. The rest of the circuit remains in

the current state, enabling fast recovery times.

If the MCU shares the SPI access with the MC33596 only, SEB control by the MCU is optional.

If not used, it could be hardwired to 0.

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SCLK — Serial clock input/output

Synchronizes data movement in and out of the device through its MOSI and MISO lines. The

master and slave devices can exchange a byte of information during a sequence of eight clock

cycles. Since SCLK is generated by the master device, this line is an input on the slave device.

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MOSI — Master output slave input/output

In configuration mode, MOSI is an input.

In receive mode, MOSI is an output. Received data is sent on MOSI (see Table 5).

When no data are output, SCLK and MOSI force a low level.

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MISO — Master input/slave output

In configuration mode only, data read from registers is sent to the MCU with the MSB first. There

is no master function. Data are valid on falling edges of SCLK. This means that the clock phase

and polarity control bits of the microcontroller SPI have to be CPOL = 0 and CPHA = 1 (using

Freescale acronyms).

Table 5 summarizes the serial digital interface feature versus the selected mode.

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