AD6642BBCZ datasheet(24/32 Pages) AD

24 / 32 page

AD6642

Rev. 0 | Page 24 of 32

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

The AD6642 includes built-in test features designed to verify

the integrity of each channel and to facilitate board-level debug-

ging. A BIST (built-in self-test) feature is included that verifies

the integrity of the digital datapath of the AD6642. Various

output test options are also provided to place predictable values

on the outputs of the AD6642.

BUILT-IN SELF-TEST (BIST)

The BIST is a thorough test of the digital portion of the selected

AD6642 signal path. When enabled, the test runs from an internal

pseudorandom noise (PN) source through the digital datapath

starting at the ADC block output. The BIST sequence runs for

512 cycles and stops. The BIST signature value for the selected

channel is written to Register 0x24 and Register 0x25. If one chan-

nel is selected, its BIST signature is written to the two registers.

If Channel A and Channel B are both selected, the results from

Channel A are written to the BIST signature registers.

The outputs are not disconnected during this test, so the PN

sequence can be observed as it runs. The PN sequence can be

continued from its last value or reset from the beginning, based

on the value programmed in Register 0x0E, Bit 2. The BIST

signature result varies based on the channel configuration.

OUTPUT TEST MODES

The output test options are shown in Table 13. When an output

test mode is enabled, the analog section of the receiver is dis-

connected from the digital back-end blocks, and the test pattern

is run through the output formatting block. Some of the test

patterns are subject to output formatting. The seed value for the

PN sequence tests can be forced if the PN reset bits are used to

hold the generator in reset mode by setting Bit 4 or Bit 5 of

analog signal (if present, the analog signal is ignored), but they

require an encode clock. For more information, see Application

Note AN-877, Interfacing to High Speed ADCs via SPI.

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