FM32L278 datasheet(13/21 Pages) RAMTRON

13 / 21 page

FM32L278/L276/L274/L272 - 3V I2C Companion

Rev. 3.0

Feb. 2009

Page 13 of 21

user desires to abort a write without altering the

memory contents, this should be done using a Start

or Stop condition prior to the 8th data bit. The figures

below illustrate a single- and multiple-writes to

memory.

Figure 12. Single Byte Memory Write

Figure 13. Multiple Byte Memory Write

Memory Read Operation

There are two types of memory read operations. They

are current address read and selective address read. In

a current address read, the FM32L27x uses the

internal address latch to supply the address. In a

selective read, the user performs a procedure to first

set the address to a specific value.

Current Address & Sequential Read

As mentioned above the FM32L27x uses an internal

latch to supply the address for a read operation. A

current address read uses the existing value in the

address latch as a starting place for the read

operation. The system reads from the address

immediately following that of the last operation.

To perform a current address read, the bus master

supplies a slave address with the LSB set to 1. This

indicates that a read operation is requested. After

receiving

the

complete

device

address,

the

FM32L27x will begin shifting data out from the

current address on the next clock. The current address

is the value held in the internal address latch.

Beginning with the current address, the bus master

can read any number of bytes. Thus, a sequential read

is simply a current address read with multiple byte

transfers. After each byte the internal address counter

will be incremented.

Each time the bus master acknowledges a byte,

this indicates that the FM32L27x should read

out the next sequential byte.

There are four ways to terminate a read operation.

Failing to properly terminate the read will most likely

create a bus contention as the FM32L27x attempts to

read out additional data onto the bus. The four valid

methods follow.

1. The bus master issues a NACK in the 9th clock

cycle and a Stop in the 10th clock cycle. This is

illustrated in the diagrams below and is

preferred.

2. The bus master issues a NACK in the 9th clock

cycle and a Start in the 10th.

3. The bus master issues a Stop in the 9th clock

cycle.

4. The bus master issues a Start in the 9th clock

cycle.

If the internal address reaches the top of memory, it

will wrap around to 0000h on the next read cycle.

The figures below show the proper operation for

current address reads.

Selective (Random) Read

There is a simple technique that allows a user to

select a random address location as the starting point

for a read operation. This involves using the first

Slave Address

Address MSB

Data Byte

By Master

By FM32L27x

Start

Address & Data

Stop

Acknowledge

Address LSB

Data Byte

Slave Address

Address MSB

Data Byte

By Master

By FM32L27x

Start

Address & Data

Stop

Acknowledge

Address LSB

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