TS4657

Application information

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4.3

Recommended power-up and power-down sequences

4.3.1

Power-up

It is recommended to power-up the TS4657 prior to applying logical data in order to ensure

correct ESD protection biasing.

When the STDBY pin is in a low state (VIL,) the circuit is in standby; when the pin is in a high

state (VIH), the circuit is enabled. An internal pull-down resistor will force the STDBY pin to

ground if no signal is applied to this pin.

The standby signal can be delayed from the power-up phase but simultaneous stimuli are

possible, as shown in Figure 51.

Figure 51.

Standby signal delayed from power-up phase

The wake-up time (Twu) of the TS4657 is defined as the time between the settlement of the

digital input signals STDBY, MCLK, BCLK, LRCLK, SDAT and 80% of the VOUTR/VOUTL

amplitude. The Twu of the circuit is typically 4.5 ms.

If all digital input signals are settled and an ON/OFF sequence is applied quickly on the

STDBY pin, the internal capacitors remain charged and the Twu is around 1 ms.

4.3.2

Power-down

As described in Section 4.2, the MCLK is internally used to supply some blocks. It is

therefore recommended not to switch off the MCLK during normal operation.

To properly power-down the device, MCLK, BCLK and LRCLK should be switched off after

the STDBY signal.

The power-down time is very short and can be considered as zero.

VCCA VCCD

STDBY

MCLK BCLK

LRCLK

t=0µs min

Twu

80%

SDAT

VOUTR VOUTL

t=0µs min

t=0µs min