3

8127CS–AVR–10/09

ATtiny4/5/9/10

2. Overview

ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

ATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per MHz, allowing the system designer

to optimize power consumption versus processing speed.

Figure 2-1.

Block Diagram

The AVR core combines a rich instruction set with 16 general purpose working registers and

system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock cycle.

The resulting architecture is compact and code efficient while achieving throughputs up to ten

times faster than conventional CISC microcontrollers.

STACK

POINTER

SRAM

PROGRAM

COUNTER

PROGRAMMING

LOGIC

ISP

INTERFACE

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

RESET FLAG

REGISTER

MCU STATUS

REGISTER

TIMER/

COUNTER0

CALIBRATED

OSCILLATOR

TIMING AND

CONTROL

INTERRUPT

UNIT

ANALOG

COMPARATOR

ADC

GENERAL

PURPOSE

REGISTERS

X

Y

Z

ALU

STATUS

REGISTER

PROGRAM

FLASH

INSTRUCTION

REGISTER

INSTRUCTION

DECODER

CONTROL

LINES

RESET

DATA REGISTER

PORT B

DIRECTION

REG. PORT B

DRIVERS

PORT B

GND

PB3:0

8-BIT DATA BUS