ATmega16 datasheet(209/357 Pages) ATMEL

209 / 357 page

209

2466S–AVR–05/09

ATmega16(L)

Figure 103. ADC Timing Diagram, Auto Triggered Conversion

Figure 104. ADC Timing Diagram, Free Running Conversion

Differential Gain

Channels

When using differential gain channels, certain aspects of the conversion need to be taken into

consideration.

Differential conversions are synchronized to the internal clock CK

ADC2 equal to half the ADC

clock. This synchronization is done automatically by the ADC interface in such a way that the

sample-and-hold occurs at a specific phase of CK

ADC2. A conversion initiated by the user (i.e., all

Table 81. ADC Conversion Time

Condition

Sample & Hold (Cycles

from Start of

Conversion)

Conversion Time (Cycles)

First conversion

13.5

Normal conversions, single ended

1.5

Auto Triggered conversions

13.5

Normal conversions, differential

1.5/2.5

13/14

MSB of Result

LSB of Result

ADC Clock

Trigger

Source

ADIF

ADCH

ADCL

Cycle Number

One Conversion

Next Conversion

Conversion

Complete

Prescaler

Reset

ADATE

Prescaler

Reset

Sample & Hold

MUX and REFS

Update

MSB of Result

LSB of Result

ADC Clock

ADSC

ADIF

ADCH

ADCL

Cycle Number

One Conversion

Next Conversion

Conversion

Complete

Sample & Hold

MUX and REFS

Update

ATmega16 데이터시트(PDF) 209 Page - ATMEL Corporation

ATmega16 데이터시트(HTML) 209 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL