AT45DB321D_09 datasheet(2/57 Pages) ATMEL

2 / 57 page

3597N–DFLASH–04/09

AT45DB321D

sequentially access its data. The simple sequential access dramatically reduces active pin

count, facilitates hardware layout, increases system reliability, minimizes switching noise, and

reduces package size. The device is optimized for use in many commercial and industrial appli-

cations where high-density, low-pin count, low-voltage and low-power are essential.

To allow for simple in-system reprogrammability, the AT45DB321D does not require high input

voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for

both the program and read operations. The AT45DB321D is enabled through the chip select pin

(CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output

(SO), and the Serial Clock (SCK).

All programming and erase cycles are self-timed.

2. Pin Configurations and Pinouts

Figure 2-1.

MLF(1) (VDFN) Top View

Note:

1. The metal pad on the bottom of the MLF

package is floating. This pad can be a “No

Connect” or connected to GND.

Figure 2-2.

SOIC Top View

Figure 2-3.

BGA Package Ball-Out (Top View)

Figure 2-4.

TSOP Top View: Type 1

Note:

TSOP package is not recommended for new designs. Future die

shrinks will support 8-pin packages only.

SCK

RESET

GND

VCC

SCK

RESET

GND

VCC

GND

SCK

RDY/BSY

RESET

RDY/BUSY

RESET

VCC

GND

SCK

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