ICS1893 datasheet(117/152 Pages) ICST

117 / 152 page

Chapter 9

Pin Diagram, Listings, and Descriptions

ICS1893 Rev C 6/6/00

June, 2000

117

ICS1893 - Release

RXCLK

SRCLK

Output

(Symbol) Receive Clock.

In Symbol Mode, the ICS1893 sources an SRCLK to a

MAC/repeater. The SRCLK synchronizes the signals on the

SRD[4:0] pins between the ICS1893 and the MAC/repeater.

The following table contrasts the SRCLK behavior when the

mode for the ICS1893 is either 10Base-T or 100Base-TX.

Note: The signal on the SRCLK pin is conditioned by the

RXTRI pin.

Table 9-6.

MAC/Repeater Interface Pins: 100M Symbol Interface (Continued)

MII Pin

Name

100M

Symbol

Name

No.

Type

Pin Description

10Base-T

100Base-TX

The SRCLK frequency is

2.5 MHz.

The SRCLK frequency is

25 MHz.

The ICS1893 generates its

SRCLK from the MDI data

stream using a digital PLL.

When the MDI data stream

terminates the PLL

continues to operate,

synchronously referenced

to the last packet received.

The ICS1893 generates its

SRCLK from the MDI data

stream while there is a

valid link (that is, either

data or IDLEs). In the

absence of a link, the

ICS1893 uses the REF_IN

clock to generate the

SRCLK.

The ICS1893 switches

between clock sources

during the period between

when its SCRS is asserted

and prior to its RXDV being

asserted. While the

ICS1893 is locking onto

the incoming data stream,

a clock phase change of

up to 360 degrees can

occur.

While the ICS1893 is

bringing up a link, a clock

phase change of up to 360

degrees can occur.

The RXCLK aligns once

per packet.

The RXCLK aligns once,

when the link is being

established.

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