AT91SAM9G45-CU datasheet(78/1159 Pages) ATMEL

78 / 1159 page

6438D–ATARM–13-Oct-09

AT91SAM9G45

• If WDRPROC = 1, only the processor reset is asserted.

The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a

processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog

Reset, and the Watchdog is enabled by default and with a period set to a maximum.

When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset

controller.

Figure 12-8. Watchdog Reset

12.4.5

Reset State Priorities

The Reset State Manager manages the following priorities between the different reset sources,

given in descending order:

• Backup Reset

• Wake-up Reset

• Watchdog Reset

• Software Reset

• User Reset

Particular cases are listed below:

• When in User Reset:

– A watchdog event is impossible because the Watchdog Timer is being reset by the

proc_nreset signal.

– A software reset is impossible, since the processor reset is being activated.

• When in Software Reset:

– A watchdog event has priority over the current state.

– The NRST has no effect.

Only if

WDRPROC = 0

SLCK

periph_nreset

proc_nreset

wd_fault

NRST

(nrst_out)

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup

= 3 cycles

Any

Freq.

RSTTYP

Any

XXX

0x2 = Watchdog Reset

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