4

5242B–SEEPR–01/09

AT34C02C

Note:

1. This parameter is ensured by characterization only.

Memory

Organization

AT34C02C, 2K Serial EEPROM: The 2K is internally organized with 16 pages of 16 bytes each.

Random word addressing requires a 8-bit data word address.

Device

Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external

device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on

page 6). Data changes during SCL high periods will indicate a start or stop condition as defined

below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which

must precede any other command (see Figure 5 on page 6).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a

read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-

ure 5 on page 6).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the

EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each

word. This happens during the ninth clock cycle.

Table 5. AC Characteristics

Applicable over recommended operating range from T

100 pF (unless otherwise noted)

Symbol

Parameter

AT34C02C

Units

Min

Max

Clock Frequency, SCL

400

kHz

Clock Pulse Width Low

1.2

µs

t

HIGH

Clock Pulse Width High

0.6

µs

Noise Suppression Time(1)

50

ns

Clock Low to Data Out Valid

0.1

0.9

µs

Time the bus must be free before a new

transmission can start(1)

1.2

µs

Start Hold Time

0.6

µs

t

SU.STA

Start Set-up Time

0.6

µs

Data In Hold Time

0

µs

Data In Set-up Time

100

ns

t

R

Inputs Rise Time(1)

300

ns

Inputs Fall Time(1)

300

ns

Stop Set-up Time

0.6

µs

t

DH

Data Out Hold Time

50

ns

Write Cycle Time

5ms

Endurance(1)

25

⋅C, Page Mode

1M

Write

Cycles