ATtiny167-ESSZ datasheet(111/282 Pages) ATMEL

111 / 282 page

111

7728D–AVR–07/09

ATtiny87/ATtiny167

Figure 12-1. 16-bit Timer/Counter1 Block Diagram(1)

Note:

1. Refer to Figure 1-2 on page 5, Table 9-6 on page 81, and Table 9-3 on page 76 for

Timer/Counter1 pin placement and description.

12.2.1

Registers

The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Reg-

ister (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the

16-bit registers. These procedures are described in the section “Accessing 16-bit Registers”

on page 112. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have

no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals

are all visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually

masked with the Timer Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown

in the figure.

ICFn (Int.Req.)

TOVn

(Int.Req.)

Clock Select

Timer/Counter

OCRnA

OCRnB

ICRn

TCNTn

Waveform

Generation

Waveform

Generation

OCnAU

OCnAV

OCnAW

OCnBU

OCnBV

OCnBW

Noise

Canceler

Fixed

TOP

Values

Edge

Detector

Control Logic

= 0

TOP

BOTTOM

Count

Clear

Direction

OCFnA

(Int.Req.)

OCFnB

(Int.Req.)

TCCRnA

TCCRnB

TCCRnC

ICPn

( From Analog Comparator Ouput )

Edge

Detector

( From Prescaler )

clk

OCnBX

OCnAX

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