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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ATtiny167-ESSZ 데이터시트(PDF) 50 Page - ATMEL Corporation |
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ATtiny167-ESSZ 데이터시트(HTML) 50 Page - ATMEL Corporation |
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50 / 282 page  50 7728D–AVR–07/09 ATtiny87/ATtiny167 Figure 6-1. Reset Circuit 6.1.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 22-4 on page 246. The POR is activated whenever Vcc is below the detection level. The POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after Vcc rise. The RESET signal is activated again, without any delay, when Vcc decreases below the detection level. Figure 6-2. MCU Start-up, RESET Tied to Vcc MCU Status Register (MCUSR) Brown-out Reset Circuit BODLEVEL [2..0] Delay Counters CKSEL[3:0] CK TIMEOUT DATA BUS Clock Generator Spike Filter Pull-up Resistor Watchdog Oscillator SUT[1:0] Power-on Reset Circuit RSTDISBL V TIME-OUT INTERNAL RESET tTOUT VPOT VPORMAX VPORMIN CC VCCRR |
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