ATtiny87-15MZ datasheet(7/282 Pages) ATMEL

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7728D–AVR–07/09

ATtiny87/ATtiny167

AVR CPU Core

2.1

Overview

This section discusses the AVR core architecture in general. The main function of the CPU

core is to ensure correct program execution. The CPU must therefore be able to access mem-

ories, perform calculations, control peripherals, and handle interrupts.

Figure 2-1.

Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with

separate memories and buses for program and data. Instructions in the Program memory are

executed with a single level pipelining. While one instruction is being executed, the next

instruction is pre-fetched from the Program memory. This concept enables instructions to be

executed in every clock cycle. The Program memory is In-System Reprogrammable Flash

memory. The fast-access Register File contains 32 x 8-bit general purpose working registers

with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)

operation. In a typical ALU operation, two operands are output from the Register File, the

operation is executed, and the result is stored back in the Register File – in one clock cycle.

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

EEPROM

Data Bus 8-bit

I/O Lines

Data

SRAM

I/O Module 2

Analog

Comparator

I/O Module1

Watchdog

Timer

I/O Module n

Interrupt

Unit

A.D.C.

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