AT68166HT datasheet(8/15 Pages) ATMEL

8 / 15 page

7843A–AERO–10/09

AT68166HT

Data Retention Mode

Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and sup-

ply current are guaranteed over temperature. The following rules insure data retention:

1. During data retention chip select CSx must be held high within V

CC to VCC -0.2V.

2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, mini-

mizing power dissipation.

3. During power-up and power-down transitions CSx and OE must be kept between V

CC +

0.3V and 70% of V

CC.

4. The RAM can begin operation > tR ns after VCC reaches the minimum operation voltages

(3V).

Figure 3. Data Retention Timing

Data Retention Characteristics

vcc

CSx

Parameter

Description

Min

Typ TA = 25⋅CMax

Unit

VCCDR

VCC for data retention

2.0

–

tCDR

Chip deselect to data retention time

0.0

–

Operation recovery time

tAVAV

(1)

TAVAV = Read cycle time.

––

ICCDR (2)

All CSx = VCC, VIN = GND/VCC.

Data retention current

–

(AT68166HT-25)

4.5

(AT68166HT-20)

(AT68166HT-18)

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