ATmega169P datasheet(265/393 Pages) ATMEL

265 / 393 page

265

8018N–AVR–08/09

ATmega169P

Table 25-1 summaries the scan registers for the external clock pin XTAL1, oscillators with

XTAL1/XTAL2 connections as well as 32kHz Timer Oscillator.

Notes:

1. Do not enable more than one clock source as main clock at a time.

2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between

the internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is

preferred.

3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock

configuration is considered fixed for a given application. The user is advised to scan the same

clock option as to be used in the final system. The enable signals are supported in the scan

chain because the system logic can disable clock options in sleep modes, thereby disconnect-

ing the Oscillator pins from the scan path if not provided.

25.5.4

Scanning the Analog Comparator

The relevant Comparator signals regarding Boundary-scan are shown in Figure 25-7. The

Boundary-scan cell from Figure 25-8 is attached to each of these signals. The signals are

described in Table 25-2.

The Comparator need not be used for pure connectivity testing, since all analog inputs are

shared with a digital port pin as well.

Figure 25-7. Analog Comparator

Table 25-1.

Scan Signals for the Oscillator(1)(2)(3)

Enable Signal

Scanned

Clock Line

Clock Option

Scanned Clock Line

when not Used

EXTCLKEN

EXTCLK (XTAL1)

External Clock

OSCON

OSCCK

External Crystal

External Ceramic Resonator

OSC32EN

OSC32CK

Low Freq. External Crystal

ACBG

BANDGAP

REFERENCE

ADC MULTIPLEXER

OUTPUT

ACME

AC_IDLE

ACO

ADCEN

ACD

ATmega169P 데이터시트(PDF) 265 Page - ATMEL Corporation

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