ATmega169P datasheet(48/393 Pages) ATMEL

48 / 393 page

8018N–AVR–08/09

ATmega169P

Figure 10-1. Reset Logic

10.2.1

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level

is defined in ”System and Reset Characteristics” on page 331. The POR is activated whenever

CC is below the detection level. The POR circuit can be used to trigger the start-up Reset, as

well as to detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

device is kept in RESET after V

CC rise. The RESET signal is activated again, without any delay,

when V

CC decreases below the detection level.

Figure 10-2. MCU Start-up, RESET Tied to V

MCU Status

Brown-out

Reset Circuit

BODLEVEL [2..0]

Delay Counters

CKSEL[3:0]

TIMEOUT

DATA BUS

Clock

Generator

SPIKE

FILTER

Pull-up Resistor

JTAG Reset

Watchdog

Oscillator

SUT[1:0]

Power-on Reset

Circuit

RESET

TIME-OUT

INTERNAL

RESET

TOUT

POT

RST

ATmega169P 데이터시트(PDF) 48 Page - ATMEL Corporation

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