ATmega325P datasheet(64/364 Pages) ATMEL

64 / 364 page

8023F–AVR–07/09

ATmega325P/3250P

Functions” on page 69. Refer to the individual module sections for a full description of the alter-

nate functions.

Note that enabling the alternate function of some of the port pins does not affect the use of the

other pins in the port as general digital I/O.

13.2

Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 shows a func-

tional description of one I/O-port pin, here generically called Pxn.

Figure 13-2. General Digital I/O

(1)

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

I/O,

SLEEP, and PUD are common to all ports.

13.2.1

Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in ”Register

Description” on page 85, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits

at the PORTx I/O address, and the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input

pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is

activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to

clk

RPx

RRx

RDx

WDx

PUD

SYNCHRONIZER

WDx:

WRITE DDRx

WRx:

WRITE PORTx

RRx:

READ PORTx REGISTER

RPx:

READ PORTx PIN

PUD:

PULLUP DISABLE

clk

I/O:

I/O CLOCK

RDx:

READ DDRx

RESET

CLR

PORTxn

CLR

DDxn

PINxn

SLEEP

SLEEP:

SLEEP CONTROL

Pxn

I/O

WPx

WRx

WPx:

WRITE PINx REGISTER

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