ATmega325P datasheet(141/364 Pages) ATMEL

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8023F–AVR–07/09

ATmega325P/3250P

16.7.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2A Register is used to

manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter

value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence

also its resolution. This mode allows greater control of the compare match output frequency. It

also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 16-5. The counter value (TCNT2)

increases until a compare match occurs between TCNT2 and OCR2A, and then counter

(TCNT2) is cleared.

Figure 16-5. CTC Mode, Timing Diagram

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is

running with none or a low prescaler value must be done with care since the CTC mode does

not have the double buffering feature. If the new value written to OCR2A is lower than the cur-

rent value of TCNT2, the counter will miss the compare match. The counter will then have to

count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match

can occur.

For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to toggle mode

(COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for

the pin is set to output. The waveform generated will have a maximum frequency of f

OC2A =

clk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following

equation:

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

TCNTn

OCnx

(Toggle)

OCnx Interrupt Flag Set

Period

(COMnx1:0 = 1)

fOCnx

clk_I/O

OCRnx

()

⋅⋅

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