ATmega32HVB datasheet(96/273 Pages) ATMEL

96 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

In 16-bit mode the OCRnB register contains the high byte of the 16-bit Output Compare Regis-

ter. To ensure that both the high and the low bytes are written simultaneously when the CPU

writes to these registers, the access is performed using an 8-bit temporary high byte register

(TEMP). This temporary register is shared by all the other 16-bit registers. See ”Accessing Reg-

isters in 16-bit Mode” on page 90.

17.10.6

TIMSKn – Timer/Counter n Interrupt Mask Register

• Bit 3 – ICIEn: Timer/Counter n Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter n Input Capture interrupt is enabled. The corresponding Interrupt

Vector (See Section “12.” on page 52.) is executed when the ICFn flag, located in TIFRn, is set.

• Bit 2 – OCIEnB: Timer/Counter n Output Compare Match B Interrupt Enable

When the OCIEnB bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if

a Compare Match in Timer/Counter occurs, i.e., when the OCFnB bit is set in the Timer/Counter

Interrupt Flag Register – TIFRn.

• Bit 1 – OCIEnA: Timer/Counter n Output Compare Match A Interrupt Enable

When the OCIEnA bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter n Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a Compare Match in Timer/Counter n occurs, i.e., when the OCFnA bit is set in the

Timer/Counter n Interrupt Flag Register – TIFRn.

• Bit 0 – TOIEn: Timer/Counter n Overflow Interrupt Enable

When the TOIEn bit is written to one, and the I-bit in the Status Register is set, the Timer/Coun-

ter n Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in

Timer/Counter n occurs, i.e., when the TOVn bit is set in the Timer/Counter n Interrupt Flag Reg-

ister – TIFRn.

17.10.7

TIFRn – Timer/Counter n Interrupt Flag Register

• Bits 3 – ICFn: Timer/Counter n Input Capture Flag

This flag is set when a capture event occurs, according to the setting of ICENn, ICESn and ICSn

bits in the TCCRnA Register.

ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,

ICFn can be cleared by writing a logic one to its bit location.

Bit

76543210

(0x6E)(0x6F)

----

ICIEn

OCIEnB

OCIEnA

TOIEn

TIMSKn

Read/Write

R/W

Initial Value

00000000

Bit

765

4321

0x15 (0x35)

---

ICFn

OCFnB

OCFnA

TOVn

TIFRn

Read/Write

RRRR

R/W

Initial Value

000

0000

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