ATmega32HVB datasheet(183/273 Pages) ATMEL

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183

8042A–AVR–07/09

ATmega16HVB/32HVB

27.9

Bus Connect/Disconnect for Two-wire Serial Interface

The Bus Connect/Disconnect module is an addition to the TWI Interface. Based on a configura-

tion bit, an interrupt can be generated either when the TWI bus is connected or disconnected.

Figure 27-22 illustrates the Bus Connect/Disconnect logic, where SDA and SCL are the TWI

data and clock lines, respectively.

When the TWI bus is connected, both the SDA and the SCL lines will become high simultane-

ously. If the TWBCIP bit is cleared, the interrupt will be executed if enabled. Once the bus is

connected, the TWBCIP bit should be set. This enables detection of when the bus is discon-

nected, and prevents repetitive interrupts every time both the SDA and SCL lines are high (e.g.

bus IDLE state).

When the TWI bus is disconnected, both the SDA and the SCL lines will become low simultane-

ously. If the TWBCIP bit is set, the interrupt will be executed if enabled and if both lines remain

low for a configurable time period. By adding this time constraint, unwanted interrupts caused by

both lines going low during normal bus communication is prevented.

Figure 27-22. Overview of Bus Connect/Disconnect.

DELAY ELEMENT

START

OUTPUT

DELAY

TWBCSR

SDA

SCL

SET TWBCIF

IRQ

TWBCIP

8-BIT DATA BUS

ATmega32HVB 데이터시트(PDF) 183 Page - ATMEL Corporation