ATmega32HVB datasheet(216/273 Pages) ATMEL

216 / 273 page

216

8042A–AVR–07/09

ATmega16HVB/32HVB

30.7

Parallel Programming

This section describes parameters, pin mapping, and commands used to parallel program and

verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the

ATmega16HVB/32HVB. Pulses are assumed to be at least 250 ns unless otherwise noted.

30.7.1

Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. For efficient

programming, the following should be considered.

• The command needs only be loaded once when writing or reading multiple memory locations.

• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the

EESAVE Fuse is programmed) and Flash after a Chip Erase.

Address high byte needs only be loaded before programming or reading a new 256 word window

in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading.

30.7.2

Signal Names

In this section, some pins of the ATmega16HVB/32HVB are referenced by signal names

describing their functionality during parallel programming, see Figure 30-3 on page 216 and

Table 30-13 on page 217. Pins not described in the following table are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.

The bit coding is shown in Table 30-15 on page 217.

When pulsing WR or OE, the command loaded determines the action executed. The different

Commands are shown in Table 30-16 on page 218. Table 32-18 on page 239 shows the Parallel

programming characteristics.

Figure 30-3. Parallel Programming

VCC

+3.0 - 3.3V

GND

DATA[7:0]

VFET

(0V)

+11.5 - 12.5V

RESET

PAGEL

BS2

BS1

XTAL1

RDY/BSY

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