ATmega16A datasheet(41/352 Pages) ATMEL

41 / 352 page

8154B–AVR–07/09

ATmega16A

ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three

conditions above to ensure that the reference is turned off before entering Power-down mode.

10.3

Watchdog Timer

The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is

the typical value at V

CC = 5V. See characterization data for typical values at other VCC levels. By

controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as

shown in Table 10-1 on page 43. The WDR – Watchdog Reset – instruction resets the Watch-

dog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.

Eight different clock cycle periods can be selected to determine the reset period. If the reset

period expires without another Watchdog Reset, the ATmega16A resets and executes from the

Reset Vector. For timing details on the Watchdog Reset, refer to page 40.

To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be fol-

lowed when the Watchdog is disabled. Refer to the description of the Watchdog Timer Control

Figure 10-7. Watchdog Timer

10.4

10.4.1

MCUCSR – MCU Control and Status Register

The MCU Control and Status Register provides information on which reset source caused an

MCU Reset.

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by

the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic

zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

WATCHDOG

OSCILLATOR

Bit

7654

321

JTD

ISC2

–

JTRF

WDRF

BORF

EXTRF

PORF

MCUCSR

Read/Write

R/W

Initial Value

See Bit Description

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