ATtiny261A datasheet(165/292 Pages) ATMEL

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8197A–AVR–10/09

ATtiny261A/461A/861A

To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and

repeat the procedure above. If successful, the contents of the destination register are as follows.

Refer to Table 18-4 on page 168 for detailed description and mapping of the Fuse High Byte.

To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and

repeat the previous procedure. If successful, the contents of the destination register are as

follows.

Refer to Table 18-3 on page 168 for detailed description and mapping of the Fuse Extended

Byte.

17.7 Preventing Flash Corruption

During periods of low VCC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and the same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low. First, a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating

voltage matches the detection level. If not, an external low VCC reset protection circuit

can be used. If a reset occurs while a write operation is in progress, the write operation

will be completed provided that the power supply voltage is sufficient.

2. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

17.8 Programming Time for Flash when Using SPM

The calibrated oscillator is used to time Flash accesses. Table 17-1 shows the typical program-

ming time for Flash accesses from the CPU.

Note:

1. Minimum and maximum programming time is per individual operation.

Bit

543

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

Bit

543

FEB7

FEB6

FEB5

FEB4

FEB3

FEB2

FEB1

FEB0

Table 17-1.

SPM Programming Time(1)

Symbol

Min Programming Time

Max Programming Time

Flash write (Page Erase, Page Write, and

write Lock bits by SPM)

3.7 ms

4.5 ms

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