ATtiny261A datasheet(28/292 Pages) ATMEL

28 / 292 page

8197A–AVR–10/09

ATtiny261A/461A/861A

When the PLL output is selected as clock source, the start-up times are determined by SUT fuse

bits as shown in Table 6-5.

6.2.3

Calibrated Internal 8 MHz Oscillator

By default, the Internal Oscillator provides an approximately 8 MHz clock signal. Though voltage

and temperature dependent, this clock can be very accurately calibrated by the user. See Table

19-2 on page 186 and “Internal Oscillators” on page 218 for more details. The device is shipped

with the CKDIV8 Fuse programmed. See “System Clock Prescaler” on page 31 for more details.

This clock may be selected as the system clock by programming the CKSEL Fuses as shown in

Table 6-6. If selected, it will operate with no external components. During reset, hardware loads

the pre-programmed calibration value into the OSCCAL Register and thereby automatically cal-

ibrates the internal oscillator. The accuracy of this calibration is shown as Factory calibration in

Table 19-2 on page 186.

Notes: 1. The device is shipped with this option selected.

2. If the oscillator frequency exceeds the specification of the device (depends on VCC), the

CKDIV8 Fuse can be programmed to divide the internal frequency by 8.

When this oscillator is selected, start-up times are determined by SUT fuses as shown in Table

6-7.

Note:

1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to

ensure programming mode can be entered.

2. The device is shipped with this option selected.

Table 6-5.

Start-up Times for the PLLCK

SUT1:0

Start-up Time from

Power Down

Additional Delay from

Power-On-Reset (VCC = 5.0V)

Recommended

usage

14CK + 1K (1024) + 4 ms

4 ms

BOD enabled

14CK + 16K (16384) + 4 ms

4 ms

Fast rising power

14CK + 1K (1024) + 64 ms

4 ms

Slowly rising power

14CK + 16K (16384) + 64 ms

4 ms

Slowly rising power

Table 6-6.

Internal Calibrated Oscillator Operating Modes

CKSEL3:0

Nominal Frequency

0010 (1)

8.0 MHz (2)

Table 6-7.

Start-up Times for the Internal Calibrated Oscillator Clock Selection

SUT1:0

Start-up Time

from Power-down

Additional Delay from

Reset (VCC = 5.0V)

Recommended

Usage

6 CK

14CK(1)

BOD enabled

6 CK

14CK + 4 ms

Fast rising power

10(2)

6 CK

14CK + 64 ms

Slowly rising power

Reserved

ATtiny261A 데이터시트(PDF) 28 Page - ATMEL Corporation

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