PD024OX8

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12.AC Characteristics

12-1 Timing conditions

Parameter

Symbol

Min.

Typ.

Max.

Unit

Delay between Hsync and DCLK

Thc

-

-

1

DCLK

Hysnc width

Twh

1

32

-

DCLK

Hysnc period

Th

60

63.5

67

s

Vsync setup time

Tvst

12

-

-

ns

Vsync hold time

Tvhd

12

-

-

ns

Hsync setup time

Thst

12

-

-

ns

Hsync hold time

Thhd

12

-

-

ns

Data set-up time

Tdsu

12

-

-

ns

Data hold time

Tdhd

12

-

-

ns

Vsync width for RGB mode

Twv

2

4

6

Th

Vsync width for YUV mode

Twv

1.5

1.5

5.5

Th

Vsync period NTSC

Tv

-

262.5

-

Th

Vsync period PAL

Tv

-

312.5

-

Th

Hsync to Vsync time for ODD field

-4

0

+4

DCLK

Hsync to Vsync time for EVEN field

0

0.5

-

Th

Serial communication

Parameter

Symbol

Min.

Typ.

Max.

Unit

Serial clock period

Tsck

320

-

-

ns

Serial clock duty cycle

Tscw

40

50

60

%

Serial clock width

Tssw

120

-

-

s

Serial data setup time

Tist

120

-

-

ns

Serial data hold time

Tihd

120

-

-

ns

SPENB setup time

Tcst

120

-

-

ns

SPENB data hold time

Tchd

120

-

-

ns

Chip select distinguish

Tcd

1

-

-

s

Delay between SPCK and Vsync

Tcv

1

-

-

s