ExpressLane

.

Features

General Features

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Forward and Reverse bridging

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Reverse bridging root functions

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Transparent bridging

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Standard 256 Plastic BGA package

(17mm x 17mm)

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Leaded and lead-free ROHS versions

available

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Low power – 2W

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No heat sink required

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EEPROM configuration option

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1.0 V core supply voltage

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DC and AC JTAG (1149.1 and

1149.6)

Scalable PCI Express Interface

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x4 Link (configurable as x1, x2 or x4)

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Full-duplex PCI Express lanes;

2.5 Gbps each

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Automatic lane reversal

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8b/10b encoding

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Link training (auto-negotiate to

smallest link width)

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256 byte maximum payload size

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PCI Express Base specification 1.0a

compliant

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End-to-end CRC and data poisoning

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Advanced error reporting

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Link and device power management

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Advanced flow control

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Hot Plug

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Turn off unused lanes for power

reduction

Advanced PCI-X Interface

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PCI-X (v 1.0b): 64 bits at 133, 100 or

66 MHz

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PCI 3.0: 32 or 64 bits at 66, 50, 33 or

25 MHz

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8-outstanding split transactions

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Internal arbiter supports up to 4

external masters

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3.3V I/O

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Message Signal Interrupt (MSI)

support

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Provides up to four PCI/PCI-X clocks

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Scratchpad and doorbell registers

Flexible, High-Performance Bridge in a Small Package

The PLX Technology ExpressLane

enables designers to migrate legacy PCI and PCI-X bus interfaces to the new

advanced serial PCI Express

reverse transparent bridging.

The bridge is equipped with a standard, but flexible PCI Express port that scales to

x1, x2 or x4 lanes with a maximum of 1 Gigabyte per second of throughput per

transmit and receive direction. With four 2.5 Gbps integrated SerDes, the standard

PCI Express signaling delivers the highest bandwidth with the lowest possible pin

count using LVDS technology.

The ExpressLane PEX 8114 has a single parallel bus segment supporting the

advanced PCI-X protocol, with a 64-bit wide parallel data path running at 133MHz.

The bridge also supports conventional PCI operation.

While both sides of the bridge are evenly matched, the device also supports internal

queues with flow control features to optimize throughput and traffic flow.

The small 17mm x 17mm footprint in standard Plastic BGA packaging makes the

ExpressLane PEX 8114 ideal for a variety of applications where board real estate is

at a premium. Leaded and lead-free ROHS versions are available.

Forward and Reverse Bridging

Compliant to the PCI Express-to-PCI/PCI-X Bridge Specification 1.0, the

ExpressLane PEX 8114 is capable of operating in either forward or reverse bridging

modes. In forward mode, the bridge allows legacy PCI or PCI-X chips and adapters

to be used with new PCI Express processor systems. Reverse bridge operation allows

conventional PCI or PCI-X processors and chipsets to configure and control

advanced PCI Express switches and endpoints. The reverse bridge not only allows

complete configuration of a downstream PCI Express system from the PCI/PCI-X

bus, but it also handles limited PCI Express root functions for reverse interrupt and

advanced error handling.

High Performance PCI Express Interface

The fully integrated PCI Express interface incorporates many of the advanced

protocol features in PCI Express such as Automatic Lane Reversal, ECRC, Data

Poisoning, Link State Power Management and Hot Plug. The single link scales from

x4 to x2 or x1 operation through configuration or automatic link training. This

enables the user to reduce power consumption by turning off unused lanes.

PEX 8114

Version 5.0 2007