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MPC5123 데이터시트(PDF) 36 Page - Freescale Semiconductor, Inc

부품명 MPC5123
상세설명  e300 Power Architecture processor core
PDF  86 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
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MPC5123 데이터시트(HTML) 36 Page - Freescale Semiconductor, Inc

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MPC5121E/MPC5123 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor
36
For Measurement and Test Conditions, see the PCI Local Bus Specification.
3.3.7
LPC
The Local Plus Bus is the external bus interface of the MPC5121e/MPC5123. A maximum of eight configurable chip selects
(CS) are provided. There are two main modes of operation: non-MUXed and MUXED. The reference clock is the LPC CLK.
The maximum bus frequency is 83 MHz.
Definition of Acronyms and Terms:
WS = Wait State
DC = Dead Cycle
HC = Hold Cycle
DS = Data Size in Bytes
BBT = Burst Bytes per Transfer
AL = Address latch enable Length
ALT = Chip select/Address Latch Timing
tLPCck = LPC clock period
4 See the timing measurement conditions in the PCI Local Bus Specification.
Table 23. LPC Timing
Sym
Description
Min
Max
Units
SpecID
tOD
CS[x], ADDR, R/W, TSIZ, DATA (wr),
TS, OE valid after LPC CLK
(Output Delay related to LPC CLK)
05
ns
A7.1
t1
Non-MUXed non-Burst CS[x] pulse
width
(2 +WS) ×tLPCck
(2 +WS) ×tLPCck
ns
A7.2
t2
ADDR, R/W, TSIZ, DATA (wr) valid
before CS[x] assertion
tLPCck –tOD
tLPCck +tOD
ns
A7.3
t3
OE assertion after CS[x] assertion
tLPCck –tOD
tLPCck +tOD
ns
A7.4
t4
ADDR, R/W, TSIZ, Data (wr) hold after
CS[x] negation
tLPCck –tOD
(HC + 1) × tLPCck +tOD
ns
A7.5
t5
TS pulse width
tLPCck
tLPCck
ns
A7.6
t6
DATA (rd) setup before LPC CLK
4
—
ns
A7.7
t7
DATA (rd) input hold
0
(DC + 1) × tLPCck
ns
A7.8
t8
Non-MUXed read Burst CS[x] pulse
width
(2 + WS + BBT/DS) × tLPCck (2 + WS + BBT/DS) × tLPCck
ns
A7.9
t9
Burst ACK pulse width
(BBT/DS) × tLPCck
(BBT/DS) × tLPCck
ns
A7.10
t10
Burst DATA (rd) input hold
0
—
ns
A7.11
t11
Read Burst ACK assertion after CS[x]
assertion
(2 +WS) ×tLPCck
(2 +WS) ×tLPCck
ns
A7.12
t12
Non-muxed write Burst CS[x] pulse
width
(2.5 + WS + BBT/DS) × tLPCck (2.5 + WS + BBT/DS) × tLPCck
ns
A7.13
t13
Write Burst ADDR, R/W, TSIZ, DATA
(wr) hold after CS[x] negation
0.5 × tLPCck –tOD
(HC + 0.5) × tLPCck +tOD
ns
A7.14



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